• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to an integrated circuit (1) for generating random signals comprising two logic gates (12, 14) whose respective outputs are connected to a first input of the other gate (14, 12) via sets of retarding elements (2i, 2j; 4i, 4j), wherein the respective delays provided by the sets of delay elements are adjustable.
    公开号:FR3023396A1
    申请号:FR1456298
    申请日:2014-07-02
    公开日:2016-01-08
    发明作者:Patrick Haddad；Viktor Fischer
    申请人:Centre National de la Recherche Scientifique CNRS；STMicroelectronics Rousset SAS；Universite Jean Monnet Saint Etienne；
    IPC主号:
    专利说明:

    [0001] BRIEF DESCRIPTION OF THE DRAWING FIELD The present description generally relates to electronic circuits and, more particularly, to integrated circuits generating non-deterministic random numbers, commonly referred to as "truly random". DISCUSSION OF THE PRIOR ART In many electronic circuits, so-called random number generators are used. In fact, it is a generation of unpredictable binary numbers, the random characteristic of the generated number being only statistical. There are many methods for checking the randomness of a number generated by an electronic circuit. These methods include, among other things, performing several draws or generations of random numbers and statistically verifying the uniformity of the distribution of the generated bits. For example, for a one-bit number, it is necessary, among other things, that the proportions of 1 and 0 generated be close. For some applications, including cryptographic applications, the non-deterministic nature of the numbers generated or randomness is important.
    [0002] B13332 - 13-R000-0866 2 A known method is to use metastable oscillations which occur in a ring composed of an even number of inverting logic gates. This phenomenon occurs when ring gates are constrained to certain values and then released. The phenomena of electronic noise impacting the delay of each of these logic gates result in the random variation over time of the number of oscillations before their stabilization. If, theoretically, such a solution is attractive, a difficulty lies in the manufacture of circuits in large series, in the guarantee of the random nature of the numbers generated. Indeed, a bad imbalance of the elements with delay does not allow the generation of unpredictable numbers. In addition, such imbalance can not be perfectly controlled during the design and manufacture of circuits. Abstract One embodiment aims at overcoming all or part of the disadvantages of the usual random number generators, based on the metastability of oscillations.
    [0003] Another embodiment aims to provide a parameterizable random number generator. Thus, an embodiment provides a random signal generating integrated circuit having two logic gates whose respective outputs are connected to a first input of the other gate via sets of delay elements, wherein the delays of the sets of delay elements are adjustable. According to one embodiment, each set of delay elements comprises a first subassembly providing a non-adjustable delay and a second subassembly providing an adjustable delay. According to one embodiment, the second subassemblies each comprise a plurality of delay elements B13332 - 13 - R000-0866 3 connected in series, the setting being effected by the number of delay elements used to convey the signals. According to one embodiment, the second subsets each comprise groups connected in parallel of delay elements, each group having a delay different from another group of the same subset, the setting of the delay provided being obtained by the selection. of the group carrying the signal. According to one embodiment, a first multiplexer 10 and a second multiplexer are interposed between the respective outputs of the second subsets of delay elements and the first respective inputs of the logic gates. According to one embodiment, the respective second inputs of the logic gates receive a control signal that triggers the generation of the random signal. One embodiment provides a random number generation circuit, comprising: an integrated circuit as above; and a digitizing circuit receiving the output of one of the sets of delay elements. According to one embodiment, the digitizing circuit comprises: an asynchronous counter whose input is connected to the output of one of the sets of delay elements; and a sampling circuit of the output of the meter. According to one embodiment, the counter comprises a number of first D type flip-flops corresponding to the number of random state bits supplied per generation period. According to one embodiment, the sampling circuit is controlled by the control signal triggering the generation of the random signal. According to one embodiment, the circuit comprises at least one circuit as above.
    [0004] B13332 - 13-R000-0866 4 BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, among which: FIG. 1 represents the equivalent electrical diagram of a usual example of a random number generator based on the metastability of oscillations in a ring composed of an even number of inverting logic gates; Figures 2A and 2B illustrate, in the form of timing diagrams, the operation of the generator of Figure 1; Fig. 3 shows an embodiment of a configurable random number generator; FIG. 4 very schematically shows in the form of blocks an example of an electronic circuit integrating a random number generator; Fig. 5 shows another embodiment of a configurable random number generator; and Figure 6 shows a variant of a digitizer circuit of a random number generator. Detailed Description The same elements have been designated by the same references in the various figures. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and will be detailed. In particular, the exploitation of the generated numbers has not been detailed, the described embodiments being compatible with the usual applications exploiting random numbers. In addition, the generation of the control signals requiring the generation of the random number has not been detailed, the described embodiments being, again, compatible with the usual digital electronic circuits. In the description which follows, when referring to the terms "about", "approximately" or "of B13332 - 13-R000-0866 the order of", this means to within 10%, preferably to within 5% . Figure 1 is a schematic representation of a random generator 1 'made in an integrated circuit. Such a generator 1 'is based on the use of two inverting logic gates (for example of the NAND type) 12 and 14 looped back on one another with the interposition of delay assemblies 22 and 42. The delay assemblies are, for example, each constituted by several retarding elements 2i or 3i (i being between 1 and N). Each delay element is, for example, a logic inverter. Each set 22, 42 brings a delay, respectively 'rA', TB ', in the propagation of the signal between the logic gates 12 and 14. In the example of FIG. 1, the respective outputs of the gates 12 and 14 are connected to the respective inputs of the assemblies 22 and 42, the outputs of which are connected to a first input of the other gate (respectively 14 and 12). The second inputs of the gates 12 and 14 are connected to an input terminal 16 of the generator 1 'intended to receive a request signal REQ for generating a random number. An output terminal 18 of the generator 1 'is connected to the output of one of the delay assemblies (in the example shown, at the output of the assembly 42) and provides a pulse train OUT in random number. The output can indifferently be taken from the output of the assembly 22. FIGS. 2A and 2B illustrate the operation of the generator 1 'of FIG. 1. FIG. 2A illustrates an example of generation of the trigger REQ signal. Fig. 2B illustrates an example of an output signal OUT.
    [0005] The signal REQ is a request signal, at rest in the low state, and which, to cause the generation of a bit, comprises a pulse whose duration is chosen so that its falling edge intervenes while the output pulse train OUT is complete, that is, the oscillations have stopped, and the reading of the present state has been made. For example, at a time t0, a rising edge is generated on the signal REQ. This rising edge is sent to the respective second inputs of the gates 12 and 14. The edge on the signal REQ then causes an observable oscillation phenomenon on the signal OUT. The presence of the sets 22 and 42 whose delays are different desynchronizes the outputs of the doors 12 and 14 relative to each other, which causes the stop oscillations. The number of oscillations before the circuit stabilizes, that is to say before the oscillation stops, depends on the internal noise of the transistors of the constituent structure of the delay elements and the gates 14 and 12. at times t1 and t1, a counting and digitizing circuit (not shown in FIG. 1) counts and stores the number of cycles (the number of rising edges or the number of falling edges) of the output signal OUT. At a time t2, preferably later or simultaneous at time t1 end of counting, the signal REQ is brought back to rest. More generally, the instant t2 must be later than the instant t1 minus the time TB ', so as to guarantee that the reading is made before the state of the terminal 18 changes by propagation of a change of state of the gate 14 under the effect of the falling edge of the signal REQ. The number of cycles of the oscillating signal is a function of the difference between the propagation delays TA 'and TB' provided by the delay assemblies 22 and 42 and is random. For the generator to be considered random, the absolute value of the difference between the delays TA 'and TB' must be between high and low limit values respectively. These limit values enclose a range of values in which the number of cycles generated has a random character. Indeed, if the difference between the delays is too small, the oscillations never stop or after a time exceeding t2-t0 and the number of cycles measured is then not at all random. If, to the contrary, the oscillations stop too quickly (difference tA '-' RB 'too important in absolute value), the randomness is not sufficient. The practical implementation of the constraints described above poses a problem in that the difference between the delays tM-TB 'varies from circuit to circuit. Indeed, this difference being related to the parameters of the transistors constituting the inverting gates of the circuit and the delay elements 22 and 42, manufacturing. Signal REQ, triggering triggering it depends on further technological dispersions, one must take care, during the generation of to define a time between its rising edges the oscillations and its falling edges generally the reading of the output signal 15 (t1 = t2) sufficient to guarantee the cessation of spontaneous oscillations in all cases, which is not always easy. FIG. 3 very schematically represents an embodiment of a random number generator based on the metastability of oscillations. As in FIG. 1, there are two NAND-type logic gates 12 and 14 whose respective first inputs receive a delayed signal from the other gate, respectively 14, 12. The output of the gate 12 drives a first signal. set 2 of delay elements. The output of the second gate 14 drives a second set 4 of delay elements. According to this embodiment, each set 2, 4 comprises a first subset or first set of N delay elements 2i, 4i, symbolized by a block 22 respectively 42. The output of the nth delay element 2i, 4i of each subassembly 22 , 42 is connected to the input of a second subset 24, respectively 44, configurable in terms of delay to the signal. It can be considered that the assemblies 22 and 42 of the generator of FIG. 1 become the subassemblies 22 and 42 of the assemblies 2 and 4 of the generator 1 of FIG. 3.
    [0006] In the example of FIG. 3, each subassembly 24, 44 has M groups of retarding elements 2i, 4i, in parallel, each group of rank j (j being between 1 and M) providing a delay corresponding to the delay elements. The respective outputs of the groups 242 and 442 are connected to M inputs of a multiplexer 244, respectively 444, M to 1. The output of the multiplexer 244 is connected to the first input of the gate 14. The output of the multiplexer 444 is connected to first input of the gate 12 and an output terminal 18 providing the oscillating signal OUT. In the example of FIG. 3, each multiplexer actually comprises M + 1 input, its row input 0 directly receiving the output of the subassembly 22, respectively 42. The respective selection inputs of the multiplexers 244 and 444 are connected, according to the addressing mode 15 (serial or parallel), to one or more CONFIG configuration signal application terminals 19 for selecting the channel or group 242, 442 of delay elements of the respective subassemblies 24 and 44 to include in the loop of the generator 1. The sets 2 and 4 respectively provide delays TA and TB which are configurable according to the number of delay elements 2j included in the signal path. FIG. 4 very schematically shows in the form of blocks an example of an electronic circuit 3 incorporating a random number generator 1 (RNG) of the type 25 described above. The signals REQ and CONFIG come from a processing unit 32. The temporarily oscillating random signal (OUT output of the circuit 1) is applied to the input of a digitizing circuit (DIG) whose output is supplied to the function (s). (block 34) using this random number. The signal REQ is applied to the circuits 1 and 5. The scanning circuit 5 may contain a synchronous counter or an asynchronous counter on several bits of the counter must be cycles) or a modulo counter 35 blocks 32 and 34 can do (in this case the last case, the number of enough to count all 2 (for example a latch T) The parts of the same circuit The signal B13332 - 13-R000-0866 9 or CONFIG configuration signals are generated, for example, from a number stored in a register 36 (REG) whose size is a function of the sum of the number of inputs of the multiplexers 244 and 444.
    [0007] Making configurable the respective delays TA and TB brought by the delay lines 2 and 3 makes it possible to configure the random generator so that its operating range is in a range where the sufficiently random generator is considered.
    [0008] Such a configuration is carried out during an initial test phase of the product incorporating the random generator and is, where appropriate, reproduced during the life of the product, for example to take into account any drifting of the parameters of the transistors.
    [0009] This configuration is done circuit by circuit. Once determined, the configuration is stored in one or more registers 36. According to an implementation mode where it is content with storage in volatile memory registers, the test phase must be repeated each time it is put into operation. route of the circuit. Therefore, it will often be preferred to store this configuration nonvolatile way. Depending on whether this configuration is likely to be modified during the lifetime of the product or not, a non-volatile reprogrammable memory or a read-only memory will be used.
    [0010] Figure 5 shows a schematic diagram of another embodiment of a random number generator 1. Compared to the embodiment of Figure 3, a difference lies in the association of the configurable delay elements. As before, one or more delay elements form first subassemblies 22, 42. However, the configurable subassemblies, here 24 'and 44', are in the form of m delay elements 2j, 4j, in series between the output of the respective subassemblies 22 and 42 and a jth input of the multiplexers 244 and 444. The M inputs of the multiplexers 244 and 444 are respectively connected to the outputs of the delay elements 2j or 4j (FIG. j being between 1 and M). Thus, the selection of the input of the multiplexer to be applied to the input of the logic gate 12, respectively 14, conditions the number of delay elements 2j or 4j used in the series association, therefore the delay TA, respectively TB, brought . FIG. 5 assumes two configuration signals CONFIG1 and CONFIG2 respectively intended for multiplexers or selectors 244 and 444. FIG. 5 also illustrates an example of a circuit 5 for digitizing the output of the generator 1. According to this example, the circuit 5 comprises two flip-flops D 52 and 54. The output Q, direct or not inverted, of the flip-flop 52 is connected, by an inverter 56, to the input D of this flip-flop 52. In a variant, the inverted output NQ of the rocker. The direct output Q is, moreover, connected to the input D of the flip-flop 54. The direct output Q of the flip-flop 54 supplies, at each falling edge of the signal REQ, a bit whose state is random. Alternatively, the inverse output NQ of flip-flop 54 can be used.
    [0011] Assuming active D flip-flops on the rising edges of their clock signals, the trigger input CLK of the flip-flop 52 is connected to the output terminal 18 of the generator 1 and the trigger input of the flip-flop 54 receives the inverse of the REQ signal. In FIG. 5, this has been symbolized by an inverter 58 connecting the terminal 16 to the CLK input of the flip-flop 54. The operation of this digitizing circuit is as follows. The state of the flip-flop 52 corresponds to the state of the low-order bit of the number of oscillations generated by the circuit 1.
    [0012] The flip-flop 52 acts as a 1-bit asynchronous counter. The flip-flop 54 samples the output of the first flip-flop 52, hence the counter, when the request signal REQ goes back down, that is to say at the end of the generation interval of a random bit.
    [0013] FIG. 6 shows another embodiment in which the generator 1 is used to generate, at each pulse of the signal REQ, an eight-bit random word. The generator 1 may be that of the embodiment 5 of FIG. 3 or that of the embodiment of FIG. 5. The digitizing circuit 5 'here comprises an eight-bit asynchronous counter whose outputs are sampled by the signal REQ. Thus, eight flip-flops D 521 to 528 (52k, with k between 1 and 8) are connected in series, the direct output Q 10 of a flip-flop of row k being looped back, by an inverter 56k to its own data input D as well as, with the exception of the last flip-flop 528, at the trigger input CLK of the next-order flip-flop. The tripping input of the first flip-flop 521 is connected to the output 18 of the generator 1. Moreover, the data input of each flip-flop 52k is connected to the data input D of a flip-flop 54k of the same rank. The direct outputs Q (or inverse NQ) of the eight flip-flops 541 to 548 each provide a random state bit at each falling edge of the signal REQ. The inverted trip inputs 20 of the flip-flops 541 to 548 are connected together to the input terminal 16 of the generator 1. The flip-flops 521 to 528 are reset by means of their reset inputs connected to a nrst terminal. . This reset occurs after time t2. More generally, the output of the generator 1 can be associated with an asynchronous or synchronous counter on any number of bits. The synchronous and asynchronous counters are differentiated by the signals triggering the flip-flops. In contrast to the architecture of an asynchronous counter, the flip-flops of a synchronous counter used in circuit 5 are all connected to the output terminal 18 of the generator. As the flip-flops of a synchronous counter are clocked by the same signal. The duration between instants t1 and 35 t2 may be shorter than that of the case of an asynchronous counter.
    [0014] B13332 - 13-R000-0866 12 The maximum operating frequency of a synchronous counter is generally lower than that of an asynchronous counter. Therefore, the choice of this second type of counter is relevant when the oscillation frequency is large. An advantage of the embodiments described above is that it is now possible to adjust the randomness of the generator to compensate for possible manufacturing dispersions.
    [0015] Another advantage is that the time interval between the rising and falling edges of the request signal can be determined more precisely. Indeed, from the moment when the delay provided by the delay elements is configured, it is possible to determine, more precisely, the necessary time interval before being sure that the oscillations stop and, consequently, to adjust the duration of the pulses of the request signal. Various embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the number of delay elements 2j and 4j of the configurable subassemblies 24 and 44 may vary. By way of a particular example, it is possible to provide a number of between ten and a thousand retarding elements 2j and 4j, preferably of the order of 128 or 256 retarding elements. A number representing a power of 2 is preferable insofar as it facilitates the realization of the multiplexers and the generation of the respective configuration signals. Likewise, the number of delay elements 2i and 4i of the fixed subassemblies 22 and 24 may vary. The NAND gates used in generator 1 may be NAND gates or combinations of NAND, OR-EXCLUSIVE, OR, AND OR NO gates. In addition, the practical implementation of the embodiments which have been described is within the abilities of those skilled in the art from the functional indications given above.
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. Integrated circuit (1) for generating random signals comprising two logic gates (12, 14) whose respective outputs are connected to a first input of the other gate (14, 12) via sets (2; ) of delay elements (2i, 2j, 4i, 4j), in which the respective delays provided by the sets of delay elements are adjustable.
    [0002]
    The circuit of claim 1, wherein each set (2; 4) of delay elements comprises a first subassembly (22; 42) providing a non-adjustable delay and a second subassembly (24; adjustable delay.
    [0003]
    3. Circuit according to claim 2, wherein the second subassemblies (24; 44) each comprise a plurality of delay elements (2j; 4j) connected in series, the setting being effected by the number of delay elements used to convey the signals.
    [0004]
    The circuit of claim 2, wherein the second subsets (24; 44) each have groups (242; 442) connected in parallel with delay elements (2j; 4j), each group having a delay different from another group of the same subset, the adjustment of the delay provided by the selection of the group carrying the signal.
    [0005]
    The circuit of any one of claims 1 to 4, wherein a first (244) and a second (444) multiplexer are interposed between the respective outputs of the second subassemblies (24; first respective inputs of the logic gates (14, 12).
    [0006]
    The circuit of any one of claims 1 to 5, wherein the respective second inputs of the logic gates (12, 14) receive a control signal (REQ) triggering the generation of the random signal.
    [0007]
    A random number generating circuit, comprising: a circuit as claimed in any one of claims 1 to 6; and a digitizing circuit (5) receiving the output of one of the sets (2; 4) of delay elements.
    [0008]
    8. Circuit according to claim 7, wherein the digitizing circuit (5) comprises: an asynchronous counter whose input is connected to the output of one of the sets (2; 4) of delay elements; and a sampling circuit of the output of the meter.
    [0009]
    The circuit of claim 8, wherein the counter has a number of first D type flip-flops (52) corresponding to the number of random state bits provided per generation period.
    [0010]
    The circuit of claim 8 or 9, as appended to claim 6, wherein the sampling circuit is controlled by the trigger command signal (REQ) of the random signal generation.
    [0011]
    An electronic circuit comprising at least one circuit according to any one of the preceding claims.
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    法律状态:
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    2017-08-18| TP| Transmission of property|Owner name: STMICROELECTRONICS (ROUSSET) SAS, FR Effective date: 20170719 |
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    2020-06-23| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1456298A|FR3023396B1|2014-07-02|2014-07-02|RANDOM NUMBER GENERATOR|FR1456298A| FR3023396B1|2014-07-02|2014-07-02|RANDOM NUMBER GENERATOR|
    US14/750,300| US10089079B2|2014-07-02|2015-06-25|Random number generator|
    US16/132,190| US10445068B2|2014-07-02|2018-09-14|Random number generator|
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